1. Field of the Invention
The present invention relates to a technique for realizing high level of integration and increase in capacity of a semiconductor memory device.
2. Description of the Background Art
FIG. 18 is a sectional view illustrating the structure of one cell of a semiconductor memory device 10P in the background art. The semiconductor memory device 10P is known as an xe2x80x9cNROMxe2x80x9d, whose description is given in xe2x80x9cExtended Abstracts of the 1999 International Conference on Solid State Devices and Materials, 1999, pp. 522-524xe2x80x9d, for example.
The semiconductor memory device 10P includes a p-type silicon substrate 20P, an ONO film 30P (consisting of silicon oxide film 30AP/silicon nitride film 30BP/silicon oxide film 30CP) and a gate electrode 40P. The ONO film 30P and the gate electrode 40P are sequentially provided in this order on the p-type silicon substrate 20P. The surface of the silicon substrate 20P includes a pair of n-type layers 51P and 52P provided therein. These n-type layers 51P and 52P are arranged in the vicinity of the ends of the ONO film 30P. In the semiconductor memory device 10P according to the background art, the ONO film 30P, the gate electrode 40P and the two n-type layers 51P, 52P constitute a cell 10CP.
In the semiconductor memory device 10P, bit judgment is performed on the basis of whether a portion 30B1P in the nitride film 30BP defined in the vicinity of the n-type layer 51P includes electrons and further, on the basis of whether a portion 30B2P in the nitride film 30BP defined in the vicinity of the n-type layer 52P includes electrons. That is, the cell 10CP of the semiconductor memory device 10P serves as a device for storing 2 bits of information.
More particularly, when a positive voltage is applied to the gate electrode 40P using the n-type layer 51P as a source and using the n-type layer 52P as a drain, a gate threshold voltage of a driving current changes on the basis of whether the portion 30B1P in the nitride film 30BP includes electrons. Conversely, when a positive voltage is applied to the gate electrode 40P using the n-type layer 51P as a drain and using the n-type layer 52P as a source, a gate threshold voltage of a driving current changes on the basis of whether the portion 30B2P in the nitride film 30BP includes electrons.
In response to the need in recent years for higher level of integration and increase in capacity to a greater degree of a semiconductor memory device, it is an object of the present invention to provide a semiconductor memory device realizing higher level of integration and increase in capacity to a greater degree as compared with the semiconductor memory device 10P in the background art.
According to the present invention, the semiconductor memory device includes a semiconductor substrate of a first conductivity type having a substrate surface, a first gate insulating film, a first gate electrode and at least four impurity layers each being of a second conductivity type opposite to the first conductivity type. The first gate insulating film is provided on the substrate surface and capable of accumulating electric charges. The first gate electrode is provided on the substrate surface through the first gate insulating film. The at least four impurity layers are provided in the substrate surface to surround the first gate insulating film in a plan view of the substrate surface.
In the semiconductor memory device, in the plan view of the substrate surface, the at least four impurity layers form a plurality of first pairs and each of the plurality of first pairs includes impurity layers opposed to each other through the first gate insulating film. Each of the plurality of first pairs serves as a source/drain of a MISFET structure including the semiconductor substrate, the first gate insulating film and the first gate electrode.
In the semiconductor memory device, the semiconductor memory device includes a plurality of (or at least two) MISFET structures provided to each first gate insulating film and first gate electrode (namely, in one cell). Therefore, as compared with the semiconductor memory device in the background art including only one MISFET structure in one cell, the number of bits to be stored in one cell is increased. As a result, it is possible to realize higher level of integration and increase in capacity to a greater degree.
Preferably, the semiconductor memory device includes a second gate insulating film, a second gate electrode and at least two impurity layers each being of the second conductivity type. The second gate insulating film is provided on the substrate surface and capable of accumulating electric charges. The second gate electrode is provided on the substrate surface through the second gate insulating film. The at least two impurity layers are provided in the substrate surface to surround the second gate insulating film together with part of the at least four impurity layers in the plan view of the substrate surface.
In the semiconductor memory device, in the plan view of the substrate surface, the at least two impurity layers and the part of the at least four impurity layers form a plurality of second pairs and each of the plurality of second pairs includes impurity layers opposed to each other through the second gate insulating film. Each of the plurality of second pairs serves as a source/drain of a MISFET structure including the substrate surface, the second gate insulating film and the second gate electrode.
In the semiconductor memory device, the MISFET structure (or cell) (including the first gate insulating film and the first gate electrode) and the MISFET structure (or cell) (including the second gate insulating film and the second gate electrode) share part of at least four impurity layers. Therefore, as compared with the structure including the cells each having the at least four impurity layers, higher level of integration is realized.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.